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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ERRIRQSR, Error Interrupt Status Register</h1><p>The ERRIRQSR characteristics are:</p><h2>Purpose</h2>
        <p>Interrupt status register.</p>
      <h2>Configuration</h2><p>This register is present only when interrupt configuration registers are implemented. Otherwise, direct accesses to ERRIRQSR are <span class="arm-defined-word">RES0</span>.</p>
        <p>ERRIRQSR is implemented only as part of a memory-mapped group of error records.</p>
      <h2>Attributes</h2>
        <p>ERRIRQSR is a 64-bit register.</p>
      <h2>Field descriptions</h2><h3>When the implementation uses the recommended layout for the ERRIRQCR registers and the implementation uses simple interrupts:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_0">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-63_0">Bits [63:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    
      <p>To determine whether an interrupt is active, software must examine the individual <a href="ext-errnstatus.html">ERR&lt;n&gt;STATUS</a> registers.</p>
    </div><h3>When the implementation uses message-signaled interrupts and the implementation uses the recommended layout for the ERRIRQCR registers:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_6">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="26"><a href="#fieldset_1-63_6">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-5_5-1">CRIERR</a></td><td class="lr" colspan="1"><a href="#fieldset_1-4_4-1">CRI</a></td><td class="lr" colspan="1"><a href="#fieldset_1-3_3-1">ERIERR</a></td><td class="lr" colspan="1"><a href="#fieldset_1-2_2-1">ERI</a></td><td class="lr" colspan="1"><a href="#fieldset_1-1_1-1">FHIERR</a></td><td class="lr" colspan="1"><a href="#fieldset_1-0_0-1">FHI</a></td></tr></tbody></table><h4 id="fieldset_1-63_6">Bits [63:6]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-5_5-1">CRIERR, bit [5]<span class="condition"><br/>When the Critical Error Interrupt is implemented:
                        </span></h4><div class="field">
      <p>Critical Error Interrupt Error.</p>
    <table class="valuetable"><tr><th>CRIERR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Critical Error Interrupt write has not returned an error since this field was last cleared to zero.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Critical Error Interrupt write has returned an error since this field was last cleared to zero.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On an Error recovery reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>Access to this field is <span class="access_level">W1C</span>.</p></div><h4 id="fieldset_1-5_5-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-4_4-1">CRI, bit [4]<span class="condition"><br/>When the Critical Error Interrupt is implemented:
                        </span></h4><div class="field">
      <p>Critical Error Interrupt write in progress.</p>
    <table class="valuetable"><tr><th>CRI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Critical Error Interrupt write not in progress.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Critical Error Interrupt write in progress.</p>
        </td></tr></table><p>Software must not disable an interrupt whilst the write is in progress.</p>
<div class="note"><span class="note-header">Note</span><p>This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.</p><p>To determine whether an interrupt is active, software must examine the individual <a href="ext-errnstatus.html">ERR&lt;n&gt;STATUS</a> registers.</p></div><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-4_4-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-3_3-1">ERIERR, bit [3]<span class="condition"><br/>When the Error Recovery Interrupt is implemented:
                        </span></h4><div class="field">
      <p>Error Recovery Interrupt Error.</p>
    <table class="valuetable"><tr><th>ERIERR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Error Recovery Interrupt write has not returned an error since this field was last cleared to zero.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Error Recovery Interrupt write has returned an error since this field was last cleared to zero.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On an Error recovery reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>Access to this field is <span class="access_level">W1C</span>.</p></div><h4 id="fieldset_1-3_3-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-2_2-1">ERI, bit [2]<span class="condition"><br/>When the Error Recovery Interrupt is implemented:
                        </span></h4><div class="field">
      <p>Error Recovery Interrupt write in progress.</p>
    <table class="valuetable"><tr><th>ERI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Error Recovery Interrupt write not in progress.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Error Recovery Interrupt write in progress.</p>
        </td></tr></table><p>Software must not disable an interrupt whilst the write is in progress.</p>
<div class="note"><span class="note-header">Note</span><p>This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.</p><p>To determine whether an interrupt is active, software must examine the individual <a href="ext-errnstatus.html">ERR&lt;n&gt;STATUS</a> registers.</p></div><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-2_2-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-1_1-1">FHIERR, bit [1]<span class="condition"><br/>When the Fault Handling Interrupt is implemented:
                        </span></h4><div class="field">
      <p>Fault Handling Interrupt Error.</p>
    <table class="valuetable"><tr><th>FHIERR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Fault Handling Interrupt write has not returned an error since this field was last cleared to zero.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Fault Handling Interrupt write has returned an error since this field was last cleared to zero.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On an Error recovery reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>Access to this field is <span class="access_level">W1C</span>.</p></div><h4 id="fieldset_1-1_1-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-0_0-1">FHI, bit [0]<span class="condition"><br/>When the Fault Handling Interrupt is implemented:
                        </span></h4><div class="field">
      <p>Fault Handling Interrupt write in progress.</p>
    <table class="valuetable"><tr><th>FHI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Fault Handling Interrupt write not in progress.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Fault Handling Interrupt write in progress.</p>
        </td></tr></table><p>Software must not disable an interrupt whilst the write is in progress.</p>
<div class="note"><span class="note-header">Note</span><p>This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.</p><p>To determine whether an interrupt is active, software must examine the individual <a href="ext-errnstatus.html">ERR&lt;n&gt;STATUS</a> registers.</p></div><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-0_0-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h3>When the implementation does not use the recommended layout for the ERRIRQCR registers:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_2-63_0">IMPLEMENTATION DEFINED</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_2-63_0">IMPLEMENTATION DEFINED</a></td></tr></tbody></table><h4 id="fieldset_2-63_0">IMPLEMENTATION DEFINED, bits [63:0]</h4><div class="field">
      <p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
    </div><h2>Accessing ERRIRQSR</h2>
        <p>If the implementation does not use the recommended layout for the ERRIRQCR registers then accesses to ERRIRQSR are <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
      <h4>ERRIRQSR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>RAS</td><td><span class="hexnumber">0xEF8</span></td><td>ERRIRQSR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When the implementation uses message-signaled interrupts, (an access is Non-secure or an access is Realm), the implementation uses the recommended layout for the ERRIRQCR registers and ERRIRQSR.NSMSI configures the physical address space for message-signaled interrupts as Secure, accesses to this register are <span class="access_level">RO</span>.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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